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STOP_MASTER Assertion during Data Burst
If the backend asserts STOP_MASTER when a DMA transfer is taking place, the core will stop the DMA transfer as
soon as possible, as shown in Figure 6-39 to Figure 6-41 on page 90 . Due to PCI protocol requirements, the core may
need to transfer one or two additional words after STOP_MASTER has been asserted. The additional data is required
to complete the PCI transfer, as when the core deasserts FRAMEN and asserts IRDYN, valid data must be provided on
the bus. See cycle nine in Figure 6-39 .
Figure 6-39 shows STOP_MASTER being asserted during a DMA read operation; in this case, no additional data is
required after STOP_MASTER is asserted. On cycles zero and one, the core reads two words of data. The first of these
words is transferred on the PCI bus on cycle four when the Target asserts TRDYN. During cycle five, the core needs to
deassert FRAMEN and assert IRDYN, since STOP_MASTER has been asserted. This can occur because the second
data word is stored in the core, allowing IRDYN to be asserted.
cycle
A0
A1
A2
A3
0
1
2
3
4
5
6
clk
framen
cben[3:0]
7
0
ad[31:0]
ADDR
0
1
par
devseln
irdyn
trdyn
stopn
reqn
gntn
mast_active
stop_master
rd_busy_master
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
0
mem_add[15:0]
mem_data_in[31:0]
0000
0
0004
1
rd_sync
Figure 6-39 · STOP_MASTER Assertion during DMA Burst Read Cycle (RD_SYNC = 0)
88
v4.0
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